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ADC-207
7-Bit, 20MHz, CMOS Flash A/D Converters
PRODUCT OVERVIEW
The ADC-207 is the industry's first 7-bit flash converter using an advanced high-speed VLSI 1.2 micron CMOS process. This process offers some very distinctive advantages over other processes, making the ADC-207 unique. The smaller geometrics of the process achieve high speed, better linearity and superior temperature performance. Since the ADC-207 is a CMOS device, it also has very low power consumption (250mW). The device draws power from a single +5V supply and is conservatively rated for 20MHz operation. The ADC-207 allows using sampling apertures as small as 12ns, making it more closely approach an ideal sampler. The small sampling apertures also let the device operate at greater than 20MHz. The ADC-207 has 128 comparators which are auto-balanced on every conversion to cancel out any offsets due to temperature and/or dynamic effects. The resistor ladder has a midpoint tap for use with an external voltage source to improve integral linearity beyond 7 bits. The ADC-207 also provides the user with 3-state outputs for easy interfacing to other components. There are six models of the ADC-207 covering two operating temperature ranges, 0 to +70C and -55 to +125C. Two high-reliability "QL" models are also available.
FEATURES

7-bit flash A/D converter 20MHz sampling rate Low power (250mW) Single +5V supply 1.2 micron CMOS technology 7-bit latched 3-state output with overflow bit Surface-mount versions High-reliability version No missing codes
AE2
AE2 AE1 CLOCK GENERATOR
ANALOG INPUT 4
R/2
AE1
1 CLOCK INPUT 10 OVERFLOW
DIP Pins 1 2 3 4 5 6
INPUT/OUTPUT CONNECTIONS FUNCTION CLOCK INPUT DIGITAL GROUND -REFERENCE ANALOG INPUT MIDPOINT +REFERENCE ANALOG GROUND CS1 CS2 OVERFLOW BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 (LSB) +5V SUPPLY
LCC Pins 1 4 5 6 7 8 9 11 12 13 14 16 17 19 20 21 23 24
+REFERENCE 6 +5V SUPPLY 18 DIGITAL GROUND 2
R +VDD R D
DQ G GQ DQ D GQ 128-TO-7 ENCODER G DQ G DQ D R/2 GQ G DQ G DQ D R GQ G DQ G DQ G
11 BIT 1 (MSB)
ANALOG GROUND 7
R/2
12 BIT 2
7 8 9 10 11
RANGE MIDPOINT 5
13 BIT 3
14 BIT 4
12 13 14 15 16
R
15 BIT 5
-REFERENCE 3
D GQ
16 BIT 6
17 18
17 BIT 7 (LSB)
CS1 8
CS2 9
Figure 1. ADC-207 Functional Block Diagram (DIP Pinout)
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MDA_ADC-207.B01 Page 1 of 6
ABSOLUTE MAXIMUM RATINGS
PARAMETERS Power Supply Voltage (+VDD) Digital Inputs Analog Input Reference Inputs Digital Outputs (short circuit protected to ground) Lead Temperature (10 sec. max.) LIMITS -0.5 to +7 -0.5 to +5.5 -0.5 to (+VDD +0.5) -0.5 to +VDD -0.5 to +5.5 +300 UNITS Volts Volts Volts Volts Volts C
PHYSICAL/ENVIRONMENTAL
PARAMETERS Operating Temp. Range, Case: LC/MC Versions MM/LM/QL Versions Storage Temp. Range Package Type DIP LCC MIN. TYP. MAX. UNITS
0 -55 -65
-- -- --
+70 +125 +150
C C C
18-pin ceramic DIP 24-pin ceramic LCC
Functional Specifications
(Typical at +5V power, +25C, 20MHz clock, +REFERENCE = +5V, -REFERENCE = ground, unless noted)
ANALOG INPUT
Input Type Input Range (dc-20MHz) Input Impedance Input Capacitance (Full Range) Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Sample Pulse Width (During Sampling Portion of Clock) Reference Ladder Resistance
MIN.
0 -- --
TYP.
MAX.
UNITS
Single-ended, non-isolated -- +5 Volts 1000 -- Ohms 10 -- pF
DIGITAL INPUTS
+3.2 -- -- -- 12 225 -- -- 1 1 -- 330 -- +0.8 5 5 -- -- Volts Volts microamps microamps ns Ohms
TECHNICAL NOTES 1. Input Buffer Amplifier - Since the ADC-207 has a switched capacitor type input, the input impedance of the 207 is dependent on the clock frequency. At relatively slow conversion rates, a general purpose type input buffer can be used; at high conversion rates DATEL recommends either the HA-5033 or Elantec 2003. See Figure 2 for typical connections. 2. Reference Ladder - Adjusting the voltage at +REFERENCE adjusts the gain of the ADC-207. Adjusting the voltage at -REFERENCE adjusts the offset or zero of the ADC-207. The midpoint pin is usually bypassed to ground through a 0.1F capacitor, although it can be tied to a precision voltage halfway between +REFERENCE and -REFERENCE. This would improve integral linearity beyond 7 bits. 3. Clock Pulse Width - To improve performance at Nyquist bandwidths, the clock duty cycle can be adjusted so that the low portion of the clock pulse is 12ns wide. The smaller aperture allows the ADC-207 to closely resemble an ideal sampler. See Figure 4. 4. At sampling rates less than 100kHz, there may be some degradation in offset and differential nonlinearity. Performance may be improved by increasing the clock duty cycle (decreasing the time spent in the sample mode). CAUTION Since the ADC-207 is a CMOS device, normal precautions against static electricity should be taken. Use ground straps, grounded mats, etc. The Absolute Maximum Ratings of the device MUST NOT BE EXCEEDED as irrevocable damage to the ADC-207 will occur.
Conversion Rate Harmonic Distortion (8MHz 2nd Order Harmonic) Differential Gain Differential Phase Aperture Delay Aperture Jitter No Missing Codes LC/MC grade LM/MM grade Integral Linearity Over Temperature Range Differential Nonlinearity Over Temperature Range Power Supply Rejection
Data Coding Data Output Resolution Logic Levels Logic "1" Logic "0" (at 1.6mA) Logic Loading "1" Logic Loading "0" Output Data Valid Delay (From Rising Edge)
PERFORMANCE 20 25 -- -- -- -- -- 0 -55 -- -- -- -- -- DIGITAL OUTPUTS 7 +2.4 -- -4 +4 -- -40 3 1.5 8 50 -- -- 0.8 1 0.3 0.4 0.02
-- -- -- -- -- -- +70 +125 1 -- 0.5 0.6 --
MHz dB % degrees ns ps C C LSB LSB LSB LSB %FSR/%Vs
0.1F +5V 20MHz CLOCK
+15 47F
4.7F + 0.01F
+
+5V
1 2 12 5 HA-5033 10 6 47F 7 11 10 W 3 4 5
CLOCK DIGITAL GND -REFERENCE VIN MID +REFERENCE ANALOG GND
+VDD B7 B6
18 17 16 15 B7 (LSB) B6 B5 B4 B3 B2 11 B1 (MSB) 10 OF
B5 14 B4 13 B3 B2 B1 OF 12
Straight binary -- --
0.1F
8 CS1 9 CS2
Bits Volts Volts mA mA ns
0.1F
+
-15
+4.5 -- -- -- 15
-- +0.4 -- -- 17
Figure 2. Typical Connections for Using the ADC-207
POWER REQUIREMENTS
Power Supply Range (+VDD) +3.0 +5.0 +5.5 Volts Power Supply Current -- +50 +70 mA Power Dissipation -- 250 385 mW Footnotes: At full power input and chip selects enabled. At 4MHz input and 20MHz clock. For 10-step, 40 IRE NTSC ramp test. Adjustable using reference ladder midpoint tap. See ADC-207 Operation.
ADC-207
7-Bit, 20MHz, CMOS Flash A/D Converters
OUTPUT CODING
(+REFERENCE = +5.12V, -REFERENCE = ground, MIDPOINT = no connection) NOTE: The reference should be held to 0.1% accuracy or better. Do not use the +5V power supply as a reference input without precision regulation and high frequency decoupling. Values shown here are for a +5.12V reference. Scale other references proportionally. Calibration equipment should test for code changes at the midpoints between these center values shown in Table 1. For example, at the half-scale major carry, set the input to 2.54V and adjust the reference until the code flickers equally between 63 and 64. Note also that the weighting for the comparator resistor network leaves the first and last thresholds within 1/2LSB of the end points to adjust the code transition to the proper midpoint values.
CLOCK AE1 AUTO ZERO AE2 SAMPLE N AE1 AUTO ZERO AE2 SAMPLE N+1 AE1 AUTO ZERO AE2 SAMPLE N+2
OUTPUT DATA
N DATA
N+1 DATA
17ns max.
17ns max.
TIMING DIAGRAM
Table 1. ADC-207 Output Coding Analog Input (Center Value) 0.00V +0.04V +1.28V +2.52V +2.56V +2.60V +3.84V +5.08V +5.12V Code Zero +1LSB +1/4FS +1/2FS - 1LSB +1/2FS +1/2FS + 1LSB +3/4FS +FS Overflow Overflow 0 0 0 0 0 0 0 0 1 1 MSB 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 2 3 4 5 6 7 LSB 0 1 0 1 0 1 0 1 1 Decimal 0 1 32 63 64 65 96 127 255* Hexadecimal (Incl. 0V) 00 01 20 3F 40 41 60 7F FF
*Note that the overflow code does not clear the data bits.
ADC-207 OPERATION
The ADC-207 uses a switched capacitor scheme in which there is an autozero phase and a sampling phase. See Figure 1 and Timing Diagram. The ADC-207 uses a single clock input. When the clock is at a high state (logic 1), the ADC-207 is in the auto-zero phase (O1). When the clock is at a low state (logic 0), the ADC-207 is in the sampling phase (O2). During phase 1, the 128 comparator outputs are shorted to their inputs through CMOS switches. This serves the purpose of bringing the inputs and outputs to the transition levels of the respective comparators. The inputs to the comparators are also connected to 128 sampling capacitors. The other end of the 128 capacitors are also shorted to 128 taps of a resistor ladder, via CMOS switches. Therefore, during phase 1 the sampling capacitors are charged to the differential voltage between a resistor tap and its respective comparator transition voltage. This eliminates offset differences between comparators and yields better temperature performance. During phase 2 (O2) the input voltage is applied to the 128 capacitors, via CMOS switches. This forces the comparators to trip either high or low. Since the comparators during phase 1 were sitting at their transition point, they can trip very quickly to the correct state. Also during phase 2, the outputs of the comparators are loaded into internal latches which in turn feed a128-to-7 encoder. When going back into phase 1, the output of the encoder is loaded into an output latch. This latch then feeds the 3-state output buffer. This means that the ADC-207 is of pipeline design. To do a single conversion, the ADC-207 requires a positive pulse followed by a negative pulse followed by a positive pulse. Continuous conversion requires one cycle/sample (one positive pulse and one negative pulse). The 3-state buffer has two enable lines, CS1 and CS2. Table 2 shows the truth table for chip select signals. CS1 has the function of enabling/disabling bits 1 through 7. CS2 has the function of enabling/disabling bits 1 through 7 and the overflow bit. Also, a full-scale input produces all ones, including the overflow bit at the output. The ADC-207 has an adjustable resistor ladder string. The top end, idle point, and bottom end are brought out for use with applications circuits. These pins are called +REFERENCE, MIDPOINT and -REFERENCE, respectively. In typical operation +REFERENCE is tied to +5V, -REFERENCE is tied to ground, and MIDPOINT is bypassed to ground. Such a configuration results in a 0 to +5V input voltage range. The MIDPOINT pin can also be tied to a +2.5V source to further improve integral linearity. This is usually not necessary unless better than 7-bit linearity is needed.
Table 2. Chip Select Truth Table
CS1 0 1 0 1 CS2 0 0 1 1 Bits 1-7 3-State Mode 3-State Mode Data Outputed 3-State Mode Overflow Bit 3-State Mode 3-State Mode Data Outputed Data Outputed
NOTE: Reduce the sample time (sample pulse) to 12ns to improve performance above 20MHz. Such a configuration will closely resemble an ideal sampler.
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MDA_ADC-207.B01 Page 3 of 6
ADC-207
7-Bit, 20MHz, CMOS Flash A/D Converters
9 8 13 12 CLOCK IN 4 5 0.01F 10pF GROUND +5 VOLTS 11
CLOCK OUT
6
20k
1 2
3
Figure 3. Optional Pulse Shaping Circuit
USING TWO ADC-207'S FOR 8-BIT RESOLUTION
Two ADC-207's (A and B) are cascadable for applications requiring 8-bit resolution. The device A provides a typical 7-bit output. The OVERFLOW signal of device A turns off device A and turns on the device B. The OVERFLOW signal of device A is also used as MSB for 8-bit operation. The device B provides the other seven bits from the input signal. Figure 4 shows the circuit connections for the application.
OVERFLOW 18 BIT 1 (MSB) 6 8 4 OPTIONAL MIDSCALE ADJUST 1 9 3 +VDD +REFERENCE CS1 OF B1 B2 B3 B4 CLOCK CS2 -REFERENCE B5 B6 B7 DIG GND 10 11 12 13 14 15 16 17 2 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 (LSB)
BEAT FREQUENCY AND ENVELOPE TESTS
Figure 5 shows an actual ADC-207 plot of the Beat Frequency Test. This test uses a 20MHz clock input to the ADC-207 with a 20.002MHz fullscale sine wave input. Although the converter would not normally be used in this mode because the input frequency violates Nyquist criteria for full recovery of signal information, the test is an excellent demonstration of the ADC-207's high-frequency performance. The effect of the 2kHz frequency difference between the input and the clock is that the output will be a 2kHz sinusoidal digital data array which "walks" along the actual input at the 2kHz beat note frequency. Any inability to follow the 20.002MHz input will be immediately obvious by plotting the digital data array. Further arithmetic analysis may be done on the data array to determine spectral purity, harmonic distortion, etc. This test is an excellent indication of: 1. Full power input bandwidth of all 128 comparators. (Any gain loss would show as signal distortion.) 2. Phase response linearity vs. instantaneous signal magnitude. (Phase problems would show as improper codes.) 3. Comparator slew rate limiting. Figure 6 shows an actual ADC-207 plot of the Envelope Test. This test is a variation of the previous test but uses a 10.002MHz sinewave input to give two overlapping cycles when the data is reconstructed by a D/A converter output to an oscilloscope. The scope is triggered by the 20MHz clock used by the A/D. Any asymmetry between positive and negative portions of the signal will be very obvious. This test is an excellent indication of slew rate capability. At the peaks of the envelope, consecutive samples swing completely through the input voltage range.
+5V +5.12 REFERENCE IN 10 TURN
ANALOG INPUT
ANALOG GROUND CLOCK IN 7 7 ANALOG GROUND ANALOG IN 6 8 1 4 9 +5V 18 3 +REFERENCE CS1 CLOCK ANALOG INPUT CS2 +VDD -REFERENCE DIG GND OF B1 B2 B3 B4 B5 B6 B7 14 15 16 17 2 10 11 12 13
REFERENCE GROUND
Figure 4. Using Two ADC-207's for 8-Bit Operation
NOTE: The output data bit numbering is offset by a bit to the device B's output.
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MDA_ADC-207.B01 Page 4 of 6
ADC-207
7-Bit, 20MHz, CMOS Flash A/D Converters
120 110 100 90 80 OUTPUT CODES 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
120 110 100 90 80 OUTPUT CODES 70 60 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
NUMBER OF SAMPLES(X103 )
NUMBER OF SAMPLES(X103 )
Figure 5. Beat Frequency Test at 20MHz
Figure 6. 10MHz Envelope Test
FFT TEST
This test actually produces an amplitude versus frequency graph (Figure 7) which indicates harmonic distortion and signal-to-noise ratio. The theoretical rms signal-to-noise ration for a 7-bit converter is +43.8dB.
70 70 65 65 60 60 55 55 50 50 45
SAMPLE PULSE = 25ns SAMPLE PULSE WIDTH = 25ns 69.2 69.2
4MHz FUNDAMENTAL 4MHz FUNDAMENTAL
AMPLITUDE (dB)
40 35 30 30 25 25 20 20 15 15 10 10 5 0 0 -5 -5 -10 -10
27.3 27.3
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
FREQUENCY (MHz)
Figure 7. FFT Test Using the ADC-207
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MDA_ADC-207.B01 Page 5 of 6
ADC-207
7-Bit, 20MHz, CMOS Flash A/D Converters
MECHANICAL DIMENSIONS INCHES (mm) 18-Pin Ceramic DIP 24-Pin Ceramic LCC
0.400 -0.005
+0.25 +0.010
(10.16 -0.13 )
0.960 MAX. (24.38 MAX.) 18 10
16 0.400 -0.005
+0.25 +0.010
24
DATEL ADC-207MC
1 PIN 1 IDENTIFIER 9
1
0.220 / 0.310 (5.59 / 7.87)
(10.16 -0.13 ) 4
TOP VIEW
10
0.090 MAX. (2.29 MAX.)
0.015 / 0.060 (0.38 /1.52) 0.200 MAX. (5.1 MAX.) 0.008 / 0.015 (0.20 / 0.38)
0.020 0.005 (0.51 0.13) 0.050 (1.270) TYP. PIN 1 INDEX
0.014 / 0.023 (0.35 / 0.58)
0.100 TYP. (2.540)
SEATING PLANE 0.035 (0.889)
0.290 / 0.320 (7.36 / 8.13)
0.250 0.005 (6.35 0.13)
0.250 0.005 (6.35 0.13)
ORDERING INFORMATION MODEL ADC-207MC ADC-207MM ADC-207MM-QL ADC-207LC ADC-207LM ADC-207LM-QL ACCESSORIES ADC-B207/208 TEMP. RANGE 0 to +70C -55 to +125C -55 to +125C 0 to +70C -55 to +125C -55 to +125C PACKAGE 18-pin DIP 18-pin DIP 18-pin DIP 24-pin CLCC 24-pin CLCC 24-pin CLCC
Evaluation Board for DIP Version (without ADC-207)
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Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000
Murata Power Solutions, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A. Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
www.murata-ps.com email: sales@murata-ps.com ISO 9001 and 14001 REGISTERED
03/20/09
Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. (c) 2009 Murata Power Solutions, Inc.
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